People screwing up on verification can mess up the whole thing." Rings true as I think of mask costs and Intel's recall. The other person said this: "People can do a design without much skill and it might mostly work right. "Being able to discover a bug via verification is the skillful part." People like me wanting to cheat it without RTL are apparently screwed lol.
BERKELEY QARC PRINTING PRO
With at least one pro on team, maybe two if mixed signal. If it's really grunt work, then all these amateurs digging into actual HDL wanting to do great things might get it done if they leverage FPGA or ASIC-proven I.P. That's actually good news and hopeful for people my research supports given stuff you worked on. "The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic."
BERKELEY QARC PRINTING SOFTWARE
Sounds like hardware equivalent of wrappers in cross-language, software development. I worried about that as it's a common problem in any domain integrating different languages or models. " There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language." The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator. Reading up on it a bit more, it sounds very promising for the future.
This is where the cosimulation that MyHDL supports is so handy. Being able to discover a bug via verification is the skillful part. But your job is more about linking together static libraries that already work. It really is like building Word with assembler. Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal. The rest of us idiots are doing straight Verilog RTL because SOC level is more about gluing a lot of different modules together with low level logic. Same goes for the RISCV stuff: They can run Chisel sims because they wrote every part of the design in Chisel. No doubt guys like Intel can use the fancy HLS tools on their SOC because they own every module in the design. Verification in the high level language would be tough work until those gaps are filled. This means you would have gaps in your HL design everywhere their stuff fits in. There's no way to use these HLS tools unless the third parties feel like writing a model for their IP in your choice of HLS tool language. Additional advantage that it's open so it can be reviewed for subversion if one is willing to invest the effort.įor SOCs that I was involved with (DSPs, mobile phone SOC, wifi SOC), you are bringing together a lot of different IP from various sources. Just like to know if it's a decent HLS tool compared to FPGA or EDA company offerings. they sell is so cheap that it's either (a) crap or (b) the result of a productive, synthesis tool (Cx). Note: I'd love for some people familiar with ASIC or FPGA design to check out Cx-Lang to see if it's good for beginners getting results on FPGA's. So, here's a few that you might have not heard of.Ĭaisson - language-based security meets HDLĬx-Lang - A statically-typed, c-like, HLL for hardware One of the more unusual uses of it was Chisel-Q for quantum computing:Ĭhisel is pretty well-known in academic, hardware community. Chisel is a nice toolkit that proved itself in the Rocket processor.
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